1. Field of the Invention
The present invention relates to a bit synchronization circuit of a selective calling receiver which circuit performs bit synchronization upon reception of a transmission signal that is modulated according to 2-value or 4-value FSK.
2. Description of the Related Art
Conventionally, in receiving the above type of digital transmission signal, bit synchronization is performed to correctly identify each bit of the received digital transmission signal. FIGS. 7 and 8 respectively show examples of a selective calling receiver and a bit synchronization circuit used therein according to the prior art. The bit synchronization circuit of FIG. 8 is disclosed in Japanese Unexamined Patent Publication No. Hei. 4-177937.
FIG. 7 is a block diagram showing the entire configuration of a conventional selective calling receiver, and FIG. 8 is a block diagram showing a detailed configuration of a bit synchronization circuit used in the receiver of FIG. 7. First, the configuration of the conventional selective calling receiver will be described with reference to FIG. 7. In FIG. 7, an antenna 7 receives a signal transmitted from a base station. An amplifier 8 amplifies the transmission signal received by the antenna 7. A demodulation section 9 demodulates the transmission signal, which is modulated according to 2-value FSK, and produces a reception digital signal 1. The reception digital signal 1, which is equivalent to a polarity-judged output signal (described later), is, for instance, a binary signal that has a logic value "1" when a received transmission signal crosses level f0 (described later) upward and has a logic value "0" when it crosses level f0 downward.
A sampling circuit 13 samples the binary reception digital signal 1 and produces transmission data or information. A data buffer 16 temporarily stores the transmission data thus obtained. A bit synchronization circuit 6 detects variation points of the reception digital signal 1 received via the sampling circuit 13. (The bit synchronization circuit 6 will be described in detail with reference to FIG. 8.) A counter circuit 14-2 detects the bit rate of the transmission signal by counting variation points of the reception digital signal 1, and corrects a clock signal to be used for internal processing so that it conforms to the bit rate of the transmission signal.
A sync signal collation circuit 17 confirms reception of a frame by collating a frame sync signal contained in the transmission data stored in the data buffer 16 with that retained by itself. A singing processing circuit 18 performs calling notification (the notification may be made in any form such as output of a singing) in response to an instruction from a CPU 21 upon reception of a calling number of the receiver itself (hereinafter referred to as "self calling number"). A singing is generated by a speaker 23. A switching detection circuit 19 detects on/off switching of a switch, such as a push-button switch, which is used for, for instance, acknowledgment of a singing.
A battery saving circuit 20 turns on power to be supplied to the amplifier 8 and the demodulation section 9 when there is a possibility that the receiver receives its own calling number. (Reception of the self calling number can be predicted from received transmission frame numbers, because the receiver is assigned its own transmission frame number.) Further, the battery saving circuit 20 turns off the power to the amplifier 8 and the demodulation circuit 9 when there is no possibility of receiving the self calling number. A decoder 67 is constituted of the above-mentioned bit synchronization circuit 6, counter circuit 14-2, sampling circuit 13, data buffer 16, sync signal collation circuit 17, singing processing circuit 18, switching detection circuit 19, and battery saving circuit 20.
A CPU 21 controls the entire selective calling receiver including the decoder 67. For example, the CPU 21 collates a received calling number temporarily stored in the data buffer 16 with the self calling number stored in an IDROM 22. When finding their coincidence, the CPU 21 instructs the singing processing circuit 18 and a LCD 24 to generate a singing and display an image, respectively. As mentioned above, the IDROM stores the self calling number. A display device (simply called "LCD") displays received information by using a liquid crystal display, for instance.
Next, the operation of the conventional selective calling receiver will be described still with reference to FIG. 7. A 2-value FSK signal transmitted from a base station is received by the antenna 7, amplified by the amplifier 8, and demodulated by the demodulation section 9, which outputs a binary reception digital signal 1 to the decoder 67. The sampling circuit 13 of the decoder 67 samples the reception digital signal 1, and outputs resulting transmission data to the data buffer 16 for temporary storage thereof.
On the other hand, the bit synchronization circuit 6 detects variation points of the reception digital signal 1 received via the sampling circuit 13 (or directly). (This operation will be described in detail with reference to FIG. 8.) Informed of the detected variation points, the counter circuit 14-2 counts those points to detect a bit rate of the transmission signal. The counter circuit 14-2 corrects a clock signal that is used for internal processing so that it conforms to the bit rate of the transmission signal.
The sync signal collation circuit 17 collates a frame sync signal that is stored in the data buffer 16 with the frame sync signal retained by the sync signal collation circuit 17. When it is confirmed that a frame has been received, the sync signal collation circuit 17 continues to store transmission data ensuing the frame sync signal in the data buffer 16, and informs the CPU 21 of the reception of the transmission data and causes the data buffer 16 to output the transmission data to the CPU 21. The CPU 21 collates a calling number contained in the transmission data with the self calling number stored in the IDROM 22. When finding their coincidence, the CPU 21 instructs the singing processing circuit 18 and the LCD 24 to generate a singing and display received information, respectively.
Next, with reference to FIG. 8, a detailed description will be made of the configuration of the conventional bit synchronization circuit 6 used in the selective calling receiver of FIG. 7. In FIG. 8, a bit-length comparison timing generation circuit 5-2 generates a timing signal 2 indicating a 1-bit length of 1,600 bps, when a reception digital signal 1 one is obtained from a signal modulated at 1,600 bps, for instance. A bit-length comparison circuit 4 compares the bit length of the timing signal 2 with that of the reception digital signal 1, and produces a variation point detection selection signal 3 indicating, by "on" or "1", that the reception digital signal 1 is one obtained from a signal modulated at 1,600 bps. A variation point detection circuit 5 detects bit variation points of the reception digital signal 1 when the variation point detection selection signal 3 is "on." The counter circuit 14-2, which is the same one shown in FIG. 7, is informed of the detected variation points.
Next, the operation of the conventional bit synchronization circuit 6 will be described with reference to FIG. 8. Where the selective calling receiver is so set as to receive a 2-value FSK transmission signal that is modulated at 1,600 bps, a timing signal 2 indicating the 1-bit length of 1,600 bps is generated. The bit-length comparison circuit 4 compares the bit length of the timing signal 2 with that of a reception digital signal 1, to check whether the reception digital signal 1 is one obtained from a signal modulated at 1,600 bps. If the result is affirmative, the bit-length comparison circuit 4 produces a variation point detection selection signal 3 of "on."
The variation point detection circuit 5 detects variation points of the reception digital signal 1 only when the variation point detection selection signal 3 is "on." The counter circuit 14-2 is informed of the detected variation points. The counter circuit 14-2 counts the variation points based on a reference clock signal, and thereby detects the bit rate of the received transmission signal. Further, the counter circuit 14-2 corrects a clock signal that is used for internal processing of the selective calling receiver so that it conforms to the bit rate of the transmission signal.
As described above, in the bit synchronization circuit of the conventional selective calling receiver, when a transmission signal modulated according to 2-value FSK is to be received, variations from 0 to 1 or 1 to 0 of a reception digital signal as a demodulation signal of the transmission signal. The counter circuit corrects a clock signal so as to produce a proper internal clock signal that conforms to the detected timing.
In recent years, to accommodate rapidly increasing demand for receivers of the above kind, 4-value FSK comes to be used for modulation of a transmission signal. However, the following problems occur if, for instance, a bit synchronization circuit similar to the above-described conventional bit synchronization circuit that is used to demodulate a transmission signal modulated according to 2-value FSK is used to demodulate a transmission signal modulated according to 4-value FSK.
Referring to FIGS. 9-11, a description will now be made of problems that are associated with a case where a transmission signal modulated according to 4-value FSK is demodulated by the prior art technique. FIG. 9 is a timing chart showing a transmission signal modulated according to 4-value FSK, an output signal obtained by polarity-judging it, and a level-judged output signal. FIG. 10 is a timing chart showing a transmission signal modulated according to 4-value FSK and changing from "00" to "11," an output signal obtained by polarity-judging it, and an output signal obtained by level-judged it. FIG. 11 is a timing chart showing a transmission signal modulated according to 4-value FSK and changing "00" to "10," an output signal obtained by polarity-judging it, and an output signal obtained by level-judging it.
The bit values of a 4-value FSK transmission signal change among "00," "01, " "10," and "11" as shown in FIG. 9. The demodulation section demodulates a 4-value FSK signal of 4 levels by dividing it into two kinds of 2-value FSK signals, and produces a polarity-judged output signal and a level-judged output signal by detecting variations in the level of each of the two 2-value FSK signals.
Where a transmission signal varies between level +3.DELTA.f and level -3.DELTA.f with level f0 being the center as shown in FIG. 9, the level of a polarity-judged output signal is inverted when the transmission signal crosses level f0 as shown in FIGS. 10 and 11. The level of a level-judged output signal is inverted between .DELTA.f and 3.DELTA.f when the transmission signal crosses level f0+2.DELTA.f or f0-2.DELTA.f.
In the above prior art technique, in dealing with a transmission signal modulated according to 2-value FSK, the counter circuit corrects a clock signal by detecting variations in the state of a polarity-judged output signal (i.e., a reception digital signal) that is obtained by detecting variations in the polarity of the transmission signal. However, in dealing with a transmission signal modulated according to 4-value FSK, bit synchronization needs to be effected by detecting variation in the states of two binary output signals obtained by demodulating, i.e., dividing the transmission signal. However, there has not yet been developed any device which can effect bit synchronization on a transmission signal modulated according to 4-value FSK. The following problems occur if the prior art technique is applied to such a transmission signal.
For example, when the bit values of a transmission signal change from "00" to "11" as shown in FIG. 10, the level of the transmission signal changes from f0-3.DELTA.f to f0+.DELTA.f. The polarity of a polarity-judged output signal to be used for bit synchronization varies being deviated (i.e., varies when level f0 is crossed) from a time point when bit synchronization should be effected (i.e., the center of the varying portion of the waveform). Thus, bit synchronization is effected at proper timing.
A pulse occurs in a binary level-judged output signal that is obtained from a transmission signal modulated according to 4-value FSK when the transmission signal changes between level f0-2.DELTA.f and level f0+2.DELTA.f. For example, when the bit values of a transmission signal change from "00" to "10" as shown in FIG. 11, the level of the transmission signal changes from f0-3.DELTA.f to f0+3.DELTA.f. Since the transmission signal changes to cover the range of f0-2.DELTA.f to f0+2.DELTA.f, a pulse is generated in the level-judged output signal, whereby a value "1", is output which has not been transmitted. That is, a pulse erroneously occurs in the level-judged output signal even at a level variation point or a crossing point of the transmission signal where a pulse should not occur. Bit synchronization would be effected erroneously based on the erroneously generated level-judged output signal.